Asian Test Symposium 2024

 The Asian Test Symposium started in 1992 at Hiroshima, Japan, as an annual symposium in the Asia Pacific region. Since then, the symposium has continued its growth and development, visiting various historic cities in Asia. This year, it is marking its 33rd anniversary in Ahmedabad, India. The walled city of Ahmedabad was founded in 1411 AD on the eastern bank of the Sabarmati. It is declared as India's first-ever UNESCO World Heritage City. In modern India, it is considered as the epicenter of Indian Semiconductor activities.

Conference Website: https://ec.nirmauni.ac.in/ats-2024/ 
History of ATS: http://www.ieee-ats.org/ 

Connect with ATS : https://www.linkedin.com/company/ats-2024 
ATS-2024 technical program will include contributed papers and contributions from invited speakers. ATS-2024 will have pre-conference-tutorials, workshops, keynotes, plenary talks, technical sessions, PhD forum, student research forum, industry forum, Women-In- Semiconductor forum and expert panels.

Contributions are invited in the following areas:
· Analog/Mixed-Signal Test
· Automatic Test Generation
· Board Test and Diagnosis
· Boundary Scan Test
· Built-In Self-Test (BIST)
· Defect-Based Test
· Delay and Performance Test
· Dependability and Functional Safety
· Design for Test (DFT)
· Diagnosis and Silicon Debug
· Economic of Test
· Failure Analysis
· Fault Modelling and Simulation
· Fault Tolerance
· GPU Test
· High-Speed I/O Test
· Low-Power IC Test
· Memory Test and Repair
· Test for MEMS and Microfluidic Systems
·Multi-/Many-core Processor Test
· Test for Nanoscale Devices and Emerging Technologies
· On-line Test
· Power/Thermal/Reliability Issues in Test
· Reconfigurable System Test
· Test for Biomedical Circuits and Systems
· RF Test
· Hardware-oriented Security and Trust
· Self-Repair
· Test for Sensors and IoT
· SiP, Stacked, 3D IC Test
· Standards in Test
· Machine Learning in Test
· Test Compression
· Test Quality
· Test Synthesis
· Validation and Verification
· Yield Analysis and Enhancement
· Test for Reversible and Quantum Circuits

Submission Link: https://cmt3.research.microsoft.com/ATS2024/Submission/Index 
Full Paper Submission Deadline: August 15
2024 Acceptance Notification: September 15, 2024
Camera-Ready Submission: November 15, 2024
All submission should be made electronically in PDF format at https://cmt3.research.microsoft.com/ATS2024/Submission/Index  A submission should contain a complete manuscript within a limit 6 pages in 10-point single-spaced double-column format, an abstract of 50-200 words. The paper must be submitted for blind review process. The template for the paper can be found here. Once a submission is accepted, the author(s) must prepare the final camera-ready manuscript in time for being included in the proceedings, and present the paper at the symposium.

Several fellowships for students, research fellows and faculty will be available.

The 33 rd IEEE Asian Test Symposium ATS-2024 Ahmedabad, Gujarat, India 17 th -20 th December, 2024 
In case of any difficulty in submission, authors may contact ats2024.nu@nirmauni.ac.in